Interview Questions
Verilog Interview Questions
Basic Verilog Questions (for Freshers)
What is Verilog and why is it used?
What is the difference between wire and reg in Verilog?
Explain the difference between blocking and non-blocking assignments.
What are the different modeling styles in Verilog?
- Dataflow
- Behavioral
- Structural
What is the difference between initial and always blocks?
How do you write a 4:1 multiplexer in Verilog?
What is the use of parameter and how is it different from localparam?
What is the purpose of timescale in Verilog?
What is the difference between posedge and negedge?
Write Verilog code for a D Flip-Flop with asynchronous reset.
Intermediate Verilog Questions (2–5 years experience)
What are synthesis and simulation in Verilog?
What coding constructs are not synthesizable?
Explain race conditions in Verilog and how to avoid them.
What is the difference between case, casex, and casez?
How do you handle latch inference in Verilog?
What is meant by a "blocking assignment causing simulation mismatch"?
How do you avoid combinational loops in Verilog?
Difference between function and task in Verilog?
How do you parameterize modules in Verilog?
How to model a finite state machine (FSM) in Verilog?
Advanced Verilog/SystemVerilog Questions (5+ years experience)
How do you write synthesizable code for a priority encoder?
How does generate block work in Verilog?
Explain the implications of using # delays in RTL code.
How do you deal with metastability in clock domain crossings?
What is the difference between packed and unpacked arrays in SystemVerilog?
How do you write assertions in SystemVerilog?
What is an interface in SystemVerilog and when should you use it?
Compare Verilog with VHDL. Which one do you prefer and why?
Describe your methodology for writing testbenches.
Have you worked with UVM (Universal Verification Methodology)? How does it relate to Verilog?
Bonus: Practical Coding Test Ideas
Write Verilog code for:
Synchronous FIFO
Parameterized N-bit counter
Gray code counter
ALU supporting ADD, SUB, AND, OR operations
Two-process FSM (Moore or Mealy)
System Verilog Interview Questions
Basic SystemVerilog Questions (Freshers / Entry-Level)
What is SystemVerilog and how is it different from Verilog?
List major enhancements SystemVerilog offers over Verilog.
What are the 4 major categories of SystemVerilog features?
- Data Types
- Interfaces
- Assertions
Object-Oriented Programming (OOP)
What is the difference between logic and reg?
Explain packed vs. unpacked arrays.
What is the difference between bit, logic, and reg types?
What is a typedef and where is it useful?
What is an enum and how is it better than define constants?
What is a struct and how is it different from a union?
What is the unique and priority keyword in case statements?
Intermediate SystemVerilog Questions (2–5 years experience)
What are the advantages of using interfaces in SystemVerilog?
What is the difference between a modport and an interface?
Explain the concept of covergroup and how it helps in functional coverage.
What are constraints and how are they used in randomization?
Difference between rand and randc?
How do you write a constraint to ensure one variable is always greater than another?
What is the difference between static and automatic variables in SystemVerilog?
Explain shallow copy vs. deep copy in SystemVerilog.
How are classes different from structs in SystemVerilog?
Describe the use of this, super, and new in SystemVerilog OOP.
Advanced SystemVerilog Questions (5+ years experience)
How is UVM related to SystemVerilog and why is it widely used?
What is the difference between assert, assume, and cover in SVA (SystemVerilog Assertions)?
What is a virtual interface and how is it used in verification?
What are virtual methods and abstract classes in SystemVerilog?
How is polymorphism used in SystemVerilog testbenches?
Explain factory pattern in UVM.
How do you use constraint inheritance in derived classes?
Explain the phases in UVM and their purpose.
What is a transaction-level modeling (TLM) port in UVM?
What is DPI (Direct Programming Interface) and where is it used?
Bonus: Coding/Practical Test Prompts
Write a SystemVerilog class with constrained random variables and generate 10 random values.
Write a basic testbench using interfaces.
Create a simple assertion to detect a signal going high for more than 3 cycles.
Create a covergroup to track valid and invalid packet sizes.
Demonstrate polymorphism using a parent class and two child classes.
Universal Verification Methodology (UVM) Interview Questions
Basic UVM Questions (Freshers / Entry-Level)
What is UVM and why is it used?
What are the key components of a UVM testbench?
What is a UVM environment (uvm_env)?
What is the difference between uvm_test, uvm_env, and uvm_component?
How do you create and run a UVM test?
What are uvm_object and uvm_component? How are they different?
Explain the UVM factory mechanism.
What is the use of uvm_config_db?
What is a sequence and sequencer in UVM?
What is the difference between build_phase and run_phase?
Intermediate UVM Questions (2–5 Years Experience)
What is a UVM agent and what are its components?
Explain the difference between active and passive agents.
How does a monitor work in UVM?
What is a scoreboard and how do you use it in UVM?
How do you connect components using TLM (Transaction-Level Modeling)?
What is a transaction in UVM and how is it represented?
Explain uvm_analysis_port and uvm_analysis_export.
How do you control stimulus using sequences and sequencers?
What are objections in UVM and why are they important?
Explain the uvm_report_* macros (e.g., uvm_info, uvm_error).
Advanced UVM Questions (5+ Years Experience)
How does the UVM factory override mechanism work?
What are UVM phases? Explain each with its order of execution.
Explain uvm_component_utils vs uvm_object_utils.
How do you implement a virtual sequence and why is it used?
How do you handle synchronization between multiple sequences?
What is phase jumping in UVM? When and why would you use it?
Describe how a scoreboard compares expected vs. actual transactions.
How can you implement a coverage-driven verification flow in UVM?
What are uvm_subscriber and its use cases?
How do you debug complex UVM environments (factory errors, phase issues, etc.)?
Practical/UVM Coding Questions
Write a simple UVM sequence that generates 10 random transactions.
Implement a basic agent (driver, monitor, sequencer) in UVM.
Create a virtual sequence that starts two sub-sequences.
Write a UVM test that overrides a default sequence using the factory.
Write code to send transactions from a sequencer to a driver.